1. Technical Field
The present invention relates to (1) a mask for use in printing solder on a substrate, (2) a wiring board production method using the mask, (3) a wiring board which is produced by this production method, (4) an electrooptical apparatus production method using the wiring board production method, (5) an electrooptical apparatus which is produced by the electrooptical apparatus production method, (6) an electronic device production method using the electrooptical apparatus production method, and (7) an electronic device which is produced by this production method.
2. Related Art
As is known in the art, a wiring board formed by mounting an IC chip on a base has a structure in which the IC chip is mounted on a base material using an ACF (Anisotropic Conductive Film). An ACF is formed, for example, as shown in reference numeral 201 in FIG. 16, by dispersing a plurality of conductive particles 203 in insulating resin 202.
When an IC chip 204 is mounted on a base 206, the ACF 201 is affixed to terminals 207 formed on the base 206 and the IC chip 204 is placed on the ACF 201, and then the IC chip 204 is pressed against the base 206 while heating; that is, it is subjected to thermal compression.
The thermal compression causes the main portion of the IC chip 204 to be fixed to the base 206 at a predetermined position due to the action of the resin 202 in the ACF 201. At the same time, a plurality of electrode terminals or bumps 208 formed on an active surface of the IC chip 204 are electrically connected to the terminals 207 formed on the base 206 via the conductive particles 203 of the ACF 201.
Electronic parts such as capacitors and resistors as well as the IC chip 204 are generally mounted on the above-described wiring board formed using the ACF 201.
Typically, such electronic parts are subjected to solder reflow for mounting on a base by soldering.
Therefore, when an electronic part such as a capacitor and an IC chip are mounted on a base, such a related-art wiring board using the ACF 201 must be subjected to two separate processes, i.e., thermal compression with respect to the ACF 201 and solder reflow, leading to a problem that the production cost increases.
In the case of solder reflow after the IC chip 204 is mounted using the ACF 201, there is another problem in that the ACF 201 which carries the IC chip 204 may be stripped off from the base 206 due to heat generated in the solder reflow process, resulting in conduction defects.
Recently, IC packages having a plurality of terminals on the bottom surface thereof, like BGA (Ball Grid Array) or CSP (Chip Sized Package), have been offered for practical use. For example, the IC packages for BGA and CSP shown in FIGS. 15(a) and 15(b) are known.
Specifically, an IC package 211 shown in FIG. 15(a) is constructed such that an IC chip 216 bonded on a surface of a circuit board 213 via bonding wires 214 is overcoated with a sealing member 217 to package the IC chip 216. A plurality of wiring lines are formed on the surface of the circuit board 213 on which the IC chip 216 is mounted, and a plurality of wiring lines are also formed on the rear side of the circuit board 213. The wiring lines formed on both sides are electrically connected with each other via through-holes (not shown) extending through the circuit board 213. On the rear side, solder bump terminals 218, each corresponding to one of the plurality of wiring lines, are formed in, for example, a lattice or a matrix.
An IC package 212 shown in FIG. 15(b) is constructed such that an IC chip 216 is bonded, that is, flip-chip bonded, via a plurality of ball electrodes 219 formed in a predetermined pattern on the front surface of a circuit board 213. The IC chip 216 is overcoated with a sealing member 217 and so is packaged. A plurality of wiring lines are formed on the rear side of the circuit board 213, and solder bump terminals 218, each corresponding to one of the wiring lines, are formed in, for example, a lattice or a matrix. The IC package 212 can be designed so that it has substantially the same size as the IC chip 216.
In the IC packages shown in FIGS. 15(a) and 15(b), the IC chip 216 is mounted on the circuit board 213, whereas another known IC package, called WCSP (Wafer-Level CSP (Chip Sized Package)), is configured such that the IC chip 216 is not mounted on the circuit board 213 but the solder bump terminals 218 are mounted directly on terminals or pads on the IC chip 216.
The structure common to IC packages including the IC package 211 shown in FIG. 15(a) and the IC package 212 shown in FIG. 15(b) is that the solder bump terminals 218 are formed on the bottom surface, that is, the large-area surface, of the IC package. Such packages having the plurality of solder bump terminals 218 on the bottom or large-area surface thereof can be electrically connected to a wiring board via the solder bump terminals 218 without a conductive adhesive element, such as an ACF. In a case where electronic parts in addition to an IC chip are mounted on a wiring board, the electronic parts and the IC chip can be mounted at the same time, thus reducing the production cost.
When an IC package having terminals on the bottom surface thereof, like BGA, is mounted on a substrate, typically, solder is deposited by printing on a plurality of terminals formed on the substrate, and the IC package, which is positioned so that the terminals of the IC package will be located on the printed solder, is mounted or placed on the substrate. The solder is melted by solder reflow or the like, and the IC package is therefore soldered onto the substrate.
When solder is printed on a plurality of terminals on a substrate, typically, a mask having openings corresponding to the terminals is placed on the substrate, and solder, e.g., cream solder, is spread out over the mask using a squeegee so that the solder is applied over the substrate terminals through the openings. The openings in the mask are generally the same size as or smaller than the substrate terminals in order that short-circuits are not caused by solder printed in the wrong position.
However, if the openings in the mask are the same as or smaller than the terminals on the substrate, the contact area between the solder applied to the substrate terminals via the openings in the mask and the substrate terminals, i.e., the conduction area, decreases, resulting in conduction defects in some cases.
The present invention has been made in view of the foregoing problems, and it is an object of the present invention to constantly ensure a sufficient contact area between the solder and a plurality of terminals formed on a substrate when the solder is printed on the terminals.